1. Field of the Invention
The invention relates to a device for evaluating a magnetic field.
2. Description of the Background Art
An integrated circuit with a bidirectional mixed signal single wire interface is known from DE 10 2005 014 133 B3, which corresponds to U.S. Pat. No. 7,586,430. Via the mixed signal single wire interface the integrated circuit can receive command information from a host and can send conditioned analog signals to the host. The integrated circuit has means for analog signal conditioning, for command detection, and for digital control. For the command detection, current detectors are used that respond to the current flowing through the interface connection, so that commands can be given even when analog signals are applied to the bus. The host is a microcontroller with an analog/digital converter. Sensors can be connected via raw signal inputs or can be situated on the integrated circuit itself. In an analog signal conditioning mode, the analog signal conditioning means is embodied to amplify and/or to filter an analog signal that comes from a sensor situated on the chip itself. In the analog signal conditioning mode, the analog signal conditioning means drive the conditioned analog signal via a connection to the bidirectional mixed signal single wire interface line.
A method for testing an integrated circuit is known from EP 1 217 630 B1, which corresponds to U.S. Pat. No. 6,937,051. A sensor with multiplex data output is known from EP 1 575 013 B1, which corresponds to U.S. Pat. No. 7,319,418, and which is incorporated herein by reference. A method for the parameter assignment of an integrated circuit configuration and an integrated circuit configuration is known from EP 0 953 848 B1, which corresponds to U.S. Pat. No. 6,968,484, which is incorporated herein by reference. A circuit configuration and a method for the serial transmission of data via a terminal contact is known from EP 2 105 750 B1, which corresponds to US 20090252210, which is incorporated herein by reference. A circuit configuration with a serial test interface and a serial testing mode method is known from EP 1 855 089 A2 and EP 1 857 827 A2, which corresponds to US 20080278891 and U.S. Pat. No. 7,761,756, respectively, and which are incorporated herein by reference.